The invention relates to a tele- and data communication system, including circuits containing data flow transfer paths and having functionality for error isolation of parts of the system. By error isolation, or henceforth below mainly called "isolation" in short, of a system part is meant that there is functionality available for preventing that an error appearing in this system part affects other system parts.
High demands are put on system reliability and disturbance frequency in tele- and data communication systems. A meantime between system failures (MTBSF) of several thousand years, and disturbancy demands for a few repairs/a thousand subscriber years is not unusual. It has turned out that attainment of such features may increase the availability on an average connection a hundredfold in a realistic system.
Among known methods for increasing availability in an electronic system may be mentioned the use of redundant units on system or component level. This results in increased hardware costs and should be minimized to the greatest possible extent.
Usual is also isolation of a part unit of circuit type on a card or on a micro chip, which traditionally provides a satisfactory availability in many systems. The development of new circuits involves, however, that many circuits obtain an increasingly comprehensive functionality which in turn involves isolation/cut off of a greater part of systems in case of error situations.
Through Swedish Patent Publication SE,B, 455 459 a method is described for error supervision and increase of the availability in a digital switch network comprising partly doubled transfer paths and means for discovering and isolating errors in transfer paths and other devices included in the network.
In U.S. Pat. No. 5,036,318 there is described a modular ISDN communication system in which error information is formed in respectively assigned dependability system sub-modules from error reports of program control modules in a job-oriented manner and are transmitted to a system dependability sub-module.
U.S. Pat. No. 4,493,076 discloses a security system for an exchange having distributed control. Exchange control is distributed among a plurality of microprocessors and in microprocessor terminal units connected to a time-division switching network. The security system is organized on three levels.
In European Patent Publication EP,A1, 0 377 249 an integrated matrix memory is described which comprises standard sub-blocks and a redundant block. Each of the standard sub-blocks comprise a fixed number of standard sub-blocks. The redundant block comprises one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path.
In European Patent Publication EP,A1 0 240 577 there is disclosed an interface unit between a redundant dual-bus and a CPU and/or a data source with control and supervision logic and several encoders/decoders, as well as several transceivers connected to the bus lines. For increasing the functional safety and flexibility of the interface unit, there is connected between the transceivers and the encoders/decoders a multiplexer via which each encoder/decoder is connectable to each transceiver.
In German Patent Publication DE,A1 36 12 730 there is described a processor system with program and data memories which are addressable in blocks, which are controlled at times or once by means of self-test or diagnose programs. The system includes a spare memory consisting of a few blocks. When an erronous memory block is indicated the processor stops accessing it and the erronous block is replaced by a faultless block of the spare memory. In this faultless block the current program modules and/or data of the erronous block are stored, or, by means of a loading or generating program, the current programs and/or data are loaded. Thereupon the block is released for access by the operating program.
According to European Patent Publication EP,A3 0 074 305 logic elements are added to a conventional decoder to allow one or more defective blocks of columns to be isolated and one or more redundant blocks of columns to be substituted. The redundant block of columns is programmed by non-volatile latches. A repair address is stored in the latches. When the decoded address to a block of columns is the same as the repair address, the redundant block of columns is selected and all other blocks of columns are de-selected. Normal column block addressing is unaffected when the decoded address is different from the repair address.
In U.S. Pat. No. 3,937,936 there is described an equipment self repair apparatus utilizing the substitution of redundant circuits for a failure in any original operating logic module. The substitution is accomplished through the use of a multiplexer unit which disconnects the faulty circuit and switches a built-in spare in its place.
In U.S. Pat. No. 3,665,174 there is described an error tolerant arithmetic logical unit which is divided into vertical bit-planes which are relatively independent, being coupled mainly for the purposes of shifts and carry propagation. The system tolerates failures and still functions correctly by reconfiguring the unit through the control of interplane connections. By inserting a spare bit-plane into the system and switching between bit-planes to bypass a failed plane, the effect of the failed plane or of a failure in a position of control logic can be eliminated.
In U.S. Pat. No. 4,279,034 there is disclosed, for use in a digital communication system, a fault detector circuit operable for removing faulty stations from the system. The disclosed circuit uses a distributed bypass isolation technique and may be used with individual stations or with groups of stations. A multi-bit delay register is connected across each station or station group and the output of the delay register is compared with the output of the parallel stations. When differences in the compared bits are detected the parallel stations are immediately isolated from the system and the bits from the delay register are placed in the system to preserve synchronism.
In U.S. Pat. No. 3,805,039 system redundancy concept is disclosed wherein the system is divided into a number of substantially identical sub-elements wherein spare ones of the sub-elements may be substituted for failed ones of the sub-elements. The sub-elements and their corresponding loads are connected in a predetermined sequence. When one of the normally functioning sub-elements fails, the sub-elements following it in the sequence are disconnected from their corresponding loads then reconnected to the next load in the sequence. The last load in the sequence is reconnected to a spare sub-element.
In European Patent Publication EP,A3 0 140 712 a data transmission system comprising a plurality of reconfiguring devices and a method of reconfiguring such devices is described. Each device has a plurality of input and output data links, the devices being connected in a ring whereby for each reconfiguring device data is received on one data input link and transferred to one data output link such that data may be passed between all the reconfiguring devices along the ring. Each device includes fault recovery means for detecting the presence of a fault in the ring, the fault recovery means in different devices cooperating to attempt to cause data to be transmitted around a sub-ring when a fault is detected, the sub-ring being constituted at least partially by one or more of the previously unused data links to enable a number of the devices to continue to communicate; and merging means for detecting that a new reconfiguring device is connected to at least one pair of previously unused data input and output links and for reconfiguring the ring to include the new device.
In European Patent Publication EP,A3, 0 171 231 there is described a multistage switching network having a number of inputs and outputs comprising a plurality of switching elements arranged in an array of at least three stages. Inner groups of the stages define a plurality of nested modules where each of the switches in an outer stage is connected to associated subordinate inner modules such that at least one set of the connections between stages is redundant.